1 Bit ALU Modules

library IEEE;
use IEEE.std_logic_1164.all;

entity mux3_1t is
port(	mux_and, mux_or, mux_fa : in std_logic;
          mux_Opcode : in std_logic_vector(1 downto 0);
          mux_result : out std_logic);
end mux3_1t;

architecture behavior of mux3_1t is
begin
	with mux_Opcode select
		 mux_Result <= mux_and after 5 ns when "00",
			     mux_or after 5 ns when "01",
			     mux_fa after 5 ns when "10",
			     'U' after 5 ns when others;
end behavior;
		

	
library IEEE;
use IEEE.std_logic_1164.all;

entity FullAdder_t is
port(fa_In1, fa_In2, fa_c_in : in std_logic;
     fa_sum, fa_c_out : out std_logic);
end FullAdder_t;

architecture behavior of FullAdder_t is
signal S1, S2, S3 : std_logic;
begin
    fa_sum <= (fa_In1 xor fa_In2 xor fa_c_in) after 5 ns;
    S1 <= (fa_In1 and fa_In2) after 5 ns;
    S2 <= (fa_In1 and fa_c_in) after 5 ns;
    S3 <= (fa_In2 and fa_c_in) after 5 ns;
    fa_c_out <= (S1 or S2 or S3) after 5 ns;
end behavior;			
		

library IEEE;
use IEEE.std_logic_1164.all;

entity alu_1bit is
port(a, b, c_in : in std_logic;
     sel : in std_logic_vector(1 downto 0);
     z : out std_logic;
     c_out : out std_logic);
end alu_1bit;

architecture behavior of alu_1bit is
component FullAdder_t
port(fa_In1, fa_In2, fa_c_in : in std_logic;
     fa_sum, fa_c_out : out std_logic);
end component;

component mux3_1T
port(mux_and, mux_or, mux_fa : in std_logic;
     mux_Opcode : in std_logic_vector(1 downto 0);
     mux_result : out std_logic);
end component;

signal s1, s2, s3: std_logic;
begin
    s1 <= a and b after 5 ns;
    s2 <= a or b after 5 ns;
    FullAdd: FullAdder_t port map(fa_In1=>a, fa_In2=>b, fa_c_in=>c_in, fa_sum=>s3, fa_c_out=>c_out);
    alumux: mux3_1T port map(mux_and=> s1, mux_or =>s2,mux_fa=>z,mux_Opcode=>sel,mux_result=>z);

end behavior;